Verilog spec has a very nasty system of macros jumping from file to file, resulting in a global macro scope. We abosolutely MUST track macro redefinitions and warn user about them. Signed-off-by: Andrew Andrianov <andrew@ncrmnt.org> |
||
|---|---|---|
| .. | ||
| Makefile.in | ||
| globals.h | ||
| ivlpp.txt | ||
| lexor.lex | ||
| main.c | ||