25 lines
556 B
Verilog
25 lines
556 B
Verilog
module top;
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reg pass;
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reg [7:0] idx;
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reg [7:0] mem [0:7];
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initial begin
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pass = 1'b1;
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// Neither no_dir or no_dir2 should exist and vsim should be a file.
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// The ivltests directory should exist.
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$readmempath("/no_dir:no_dir2:vsim:ivltests");
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$readmemh("pr2509349.txt", mem);
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for (idx = 0; idx < 8; idx = idx + 1) begin
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if (mem[idx] !== idx) begin
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$display("Failed mem[%0d], expected %d, got %d", idx, idx, mem[idx]);
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pass = 1'b0;
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end
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end
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if (pass) $display("PASSED");
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end
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endmodule
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