58 lines
908 B
Verilog
58 lines
908 B
Verilog
module main;
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logic [7:0] a [0:3];
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real r [0:1];
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integer idx;
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integer errors;
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initial begin
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errors = 0;
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a[0] = 8'h11;
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a[1] = 8'h22;
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a[2] = 8'h33;
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a[3] = 8'h44;
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r[0] = 1.25;
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r[1] = 2.50;
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idx = 2;
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a[idx] = 8'haa;
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idx = 4;
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a[idx] = 8'hff;
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idx = -1;
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a[idx] <= 8'hee;
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idx = 5;
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repeat (2) a[idx] = 8'h77;
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idx = 3;
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r[idx] <= 9.50;
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idx = 'bx;
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a[idx] = 8'h66;
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idx = 'bz;
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a[idx] <= 8'h55;
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idx = 'bx;
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r[idx] = 7.25;
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#1;
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if (a[0] !== 8'h11) errors = errors + 1;
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if (a[1] !== 8'h22) errors = errors + 1;
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if (a[2] !== 8'haa) errors = errors + 1;
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if (a[3] !== 8'h44) errors = errors + 1;
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if (r[0] != 1.25) errors = errors + 1;
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if (r[1] != 2.50) errors = errors + 1;
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if (errors) begin
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$display("FAILED");
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$finish(1);
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end
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$display("PASSED");
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end
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endmodule
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