iverilog

History

Cary R 13fb07dc17 Add support for only two variable delays and add delay checks. This patch adds checks that the delay count is correct for the various gates and adds support for a missing variable decay time. For this case the decay time is the minimum of the rise and fall times. This is denoted by setting the decay variable to 0 in the vvp file. vvp notes this and sets an ignore decay time property in the base delay. This turns off the ability to set the decay time and the minimum delay calculation will also update the decay time.		2010-07-13 18:23:16 -07:00
..
Makefile.in	Update all Makefile.in files to support OpenSolaris	2010-05-13 18:54:09 -07:00
README.txt	tgt-vvp generates code that skips nets as inputs.	2001-08-10 00:40:45 +00:00
draw_mux.c	We have already verified that we have a 64 bit immediate value.	2010-07-13 16:25:19 -07:00
draw_net_input.c	Add unlimited tail recursion for the real ternary operator.	2010-07-11 17:24:37 -07:00
draw_switch.c	Push tranif delays to the code generator.	2010-07-13 16:04:05 -07:00
draw_ufunc.c	Remove malloc.h support and for C++ files use <c...> include files.	2010-06-01 08:56:30 -07:00
draw_vpi.c	Remove malloc.h support and for C++ files use <c...> include files.	2010-06-01 08:56:30 -07:00
eval_bool.c	Remove malloc.h support and for C++ files use <c...> include files.	2010-06-01 08:56:30 -07:00
eval_expr.c	Add unlimited tail recursion for the real ternary operator.	2010-07-11 17:24:37 -07:00
eval_real.c	Add unlimited tail recursion for the real ternary operator.	2010-07-11 17:24:37 -07:00
modpath.c	Fix for initial value propagation (part 1).	2010-04-13 19:22:21 -07:00
vector.c	Fix shadow warnings found on OpenBSD.	2010-05-28 07:03:02 -07:00
vvp-s.conf.in	Remove redundant back-end selections.	2008-09-07 16:43:54 -07:00
vvp.c	Add support for passing the delay selection to vvp.	2010-03-16 15:43:06 -07:00
vvp.conf.in	Remove redundant back-end selections.	2008-09-07 16:43:54 -07:00
vvp_config.h.in	Remove malloc.h support and for C++ files use <c...> include files.	2010-06-01 08:56:30 -07:00
vvp_priv.h	Add unlimited tail recursion for the real ternary operator.	2010-07-11 17:24:37 -07:00
vvp_process.c	Remove malloc.h support and for C++ files use <c...> include files.	2010-06-01 08:56:30 -07:00
vvp_scope.c	Add support for only two variable delays and add delay checks.	2010-07-13 18:23:16 -07:00

README.txt

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.


GENERAL FUNCTOR WEB STRUCTURE

The net of gates, signals and resolvers is formed from the input
design. The basic structure is wrapped around the nexus, which is
represented by the ivl_nexus_t.

Each nexus represents a resolved value. The input of the nexus is fed
by a single driver. If the nexus in the design has multiple drivers,
the drivers are first fed into a resolver (or a tree of resolvers) to
form a single output that is the nexus.

The nexus, then, feeds its output to the inputs of other gates, or to
the .net objects in the design.