62 lines
1.5 KiB
C++
62 lines
1.5 KiB
C++
/*
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* Copyright (c) 1998 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: Module.cc,v 1.1 1998/11/03 23:28:51 steve Exp $"
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#endif
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# include "Module.h"
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# include "PWire.h"
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void Module::add_gate(PGate*gate)
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{
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gates_.push_back(gate);
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}
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void Module::add_wire(PWire*wire)
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{
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wires_.push_back(wire);
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}
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void Module::add_behavior(PProcess*b)
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{
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behaviors_.push_back(b);
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}
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PWire* Module::get_wire(const string&name)
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{
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for (list<PWire*>::iterator cur = wires_.begin()
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; cur != wires_.end()
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; cur ++ ) {
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if ((*cur)->name == name)
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return *cur;
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}
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return 0;
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}
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/*
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* $Log: Module.cc,v $
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* Revision 1.1 1998/11/03 23:28:51 steve
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* Introduce verilog to CVS.
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*
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*/
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