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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
17 lines
291 B
VHDL
17 lines
291 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity or_gate is
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port (
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a_i : in std_logic; -- inputs
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b_i : in std_logic;
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c_o : out std_logic -- output
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);
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end entity or_gate;
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architecture rtl of or_gate is
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begin
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c_o <= a_i or b_i;
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end architecture rtl;
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