mirror of
https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
98 lines
2.4 KiB
Verilog
98 lines
2.4 KiB
Verilog
/*
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* Copyright (c) 2000 Stephen Williams ([email protected])
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This program tests that a non-integer delay gets its extra
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* precision accounted for if the timescale supports it. In this
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* example, set the units to 1ms, but set the precision so that the
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* numbers can be given accurate to .1ms. This should cause a delay
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* of 2.4 and 2.6 to really be different.
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*/
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`timescale 1ms / 100us
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module main;
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reg err;
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reg clk;
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reg out1, out2;
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realtime time1;
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realtime time2;
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real eps;
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always @(posedge clk) #2.4 begin
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$display($time,,$realtime, " set out1 == 1");
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time1 = $realtime;
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out1 = 1;
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end
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always @(posedge clk) #2.6 begin
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$display($time,,$realtime, " set out2 == 1");
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time2 = $realtime;
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out2 = 1;
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end
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initial begin
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clk = 0;
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out1 = 0;
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out2 = 0;
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time1 = 0;
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time2 = 0;
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err = 0;
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$timeformat(-3,1,"ms",5);
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#1 if (out1 !== 0) begin
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$display("Error -- out1 s/b 0 at time $time but is=%x", out1);
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err =1 ;
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end
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clk = 1;
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#3 if (out1 !== 1) begin
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$display("Error -- out1 s/b 1 at time $time but is=%x", out1);
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err =1 ;
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end
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eps = time1 - 3.4;
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if (eps < 0.0)
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eps = 0.0 - eps;
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if (eps > 0.0001) begin
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$display("Error -- time1 s/b 3.4 but is=%t", time1);
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err =1 ;
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end
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#1 eps = time2 - 3.6;
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if (eps < 0.0)
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eps = 0.0 - eps;
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if (eps > 0.0001) begin
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$display("Error -- time2 s/b 3.6 but is=%t, ", time2);
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err =1 ;
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end
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if(err == 0)
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$display("PASSED");
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else
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$display("FAILED");
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end // initial begin
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endmodule // main
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