Files
iverilog/ivtest/ivltests/task_nonansi_real1.v
T
Lars-Peter Clausen db33dbfbcc Add regression tests for task non-ANSI port declarations
Check that it is possible to define the data type of a non-ANSI task port
in a separate declaration from the port direction. Add tests for both the
type declared before the port direction and for the type declared after the
port direction.

Signed-off-by: Lars-Peter Clausen <[email protected]>
2022-03-16 09:17:55 +01:00

19 lines
346 B
Verilog

// Check that it is possible to declare the data type for a real type task port
// separately from the direction for non-ANSI style port declarations.
module test;
task t;
input x;
real x;
if (x == 1.23) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t(1.23);
endmodule