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Lars-Peter Clausen
35c69366a5
Check that it is not possible to declare a variable in a package without an explicit data type for the variable. Signed-off-by: Lars-Peter Clausen <[email protected]>
7 lines
179 B
Verilog
7 lines
179 B
Verilog
// Check that it is not possible to declare a variable in a package without an explicit data
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// type for the variable.
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pacakge P;
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[3:0] x; // This is a syntax error
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endpackage
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