mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
39 lines
831 B
Verilog
39 lines
831 B
Verilog
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/*
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* This tests a trivial class. This tests that properties can be
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* given types, and that the types behave properly.
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*/
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program main;
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// Trivial example of a class
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class foo_t ;
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byte signed a;
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byte unsigned b;
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endclass : foo_t // foo_t
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foo_t obj;
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initial begin
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obj = new;
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// This is the most trivial assignment of class properties.
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obj.a = 'hfff;
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obj.b = 'hfff;
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if (obj.a != -1 || obj.b != 255) begin
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$display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
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$finish;
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end
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obj.a = obj.a + 1;
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obj.b = obj.b + 1;
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if (obj.a != 0 || obj.b != 0) begin
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$display("FAILED -- increment properties: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endprogram // main
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