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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
28 lines
799 B
Verilog
28 lines
799 B
Verilog
// This tests system functions available for packed structures
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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module test;
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typedef struct packed {
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logic [7:0] high;
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logic [7:0] low;
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} word_t;
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// Declare word0 as a VARIABLE
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word_t word0;
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// error counter
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bit err = 0;
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initial begin
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if ($bits(word0 ) !== 16) begin $display("FAILED -- $bits(word0 ) = %d", $bits(word0 )); err=1; end
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if ($bits(word0.high) !== 8) begin $display("FAILED -- $bits(word0.high) = %d", $bits(word0.high)); err=1; end
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if ($bits(word0.low ) !== 8) begin $display("FAILED -- $bits(word0.low ) = %d", $bits(word0.low )); err=1; end
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if (!err) $display("PASSED");
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end
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endmodule // test
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