mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
110 lines
2.8 KiB
Verilog
110 lines
2.8 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson ([email protected])
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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//
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// SDW - Memory array instantiation, validation
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//
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// D: First do the declaration, and assignment of bit wide arrays
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// D: and 16 bit wide 4 deep arrays. Then assign values and validate
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// D: the assignment worked.
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module main();
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reg mem_1 [1:0]; // Define 2 locations, each 1 bit in depth
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reg [15:0] mem_2 [3:0]; // Define a 16 bit wide array - 4 in depth
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reg [15:0] work16;
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reg work1;
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initial // Excitation block
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begin
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mem_1 [0] = 0; // Do the initial assignment of values
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mem_1 [1] = 1;
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mem_2 [0] = 16'h0;
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mem_2 [1] = 16'h1;
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mem_2 [2] = 16'h2;
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mem_2 [3] = 16'h3;
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#5 ;
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mem_1 [1] = mem_1 [0] ; // use the mem array on the rhs
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mem_2 [3] = mem_2 [0] ;
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#5;
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end
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initial // Validation block
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begin
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#1 ;
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// Validate initialization
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work1 = mem_1[0];
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if(work1 != 0)
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begin
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$display("FAILED - mem_1 [0] init failed\n");
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$finish ;
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end
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work1 = mem_1[1];
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if(work1 != 1)
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begin
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$display("FAILED - mem_1 [1] init failed\n");
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$finish ;
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end
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work16 = mem_2 [0];
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if(work16 != 16'h0)
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begin
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$display("FAILED - mem_2 [0] init failed\n");
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$finish ;
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end
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work16 = mem_2 [1];
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if(work16 != 16'h1)
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begin
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$display("FAILED - mem_2 [1] init failed\n");
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$finish ;
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end
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work16 = mem_2 [2];
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if(work16 != 16'h2)
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begin
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$display("FAILED - mem_2 [2] init failed\n");
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$finish ;
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end
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work16 = mem_2 [3];
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if(work16 != 16'h3)
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begin
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$display("FAILED - mem_2 [3] init failed\n");
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$finish ;
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end
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#5 ;
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work1 = mem_1[1];
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if(work1 != 0)
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begin
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$display("FAILED - mem_1 [1] rhs assignment \n");
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$finish ;
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end
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work16 = mem_2 [3];
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if(work16 != 16'h0)
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begin
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$display("FAILED - mem_2 [3] rhs assignment\n");
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$finish ;
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end
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$display("PASSED\n");
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$finish ;
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end
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endmodule
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