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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
15 lines
356 B
Verilog
15 lines
356 B
Verilog
module top;
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reg [2:0] delay;
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integer lp;
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initial begin
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lp = 0;
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delay = 3'b000;
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// The delay+4 expression was failing because probe_expr_width() was
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// not called before elab_and_eval() with an expression width of -1.
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repeat (delay+4) lp = lp + 1;
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if (lp != 4) $display("FAILED");
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else $display("PASSED");
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end
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endmodule
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