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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
30 lines
540 B
Verilog
30 lines
540 B
Verilog
// This test program shows how programs can be instantiated
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// within another module.
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program test(input [7:0] sh1, input [7:0] sh2);
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final begin
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if (sh1 !== 'h55) begin
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$display("FAILED -- shared=%b is not correct", sh1);
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$finish;
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end
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if (sh2 !== 'haa) begin
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$display("FAILED -- sh2 not correct", sh2);
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$finish;
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end
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$display("PASSED");
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end
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endprogram :test
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module main;
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reg[7:0] shared = 'h55;
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wire [7:0] not_shared = ~shared;
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test check(shared, not_shared);
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endmodule // main
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