mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-28 16:53:45 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
32 lines
589 B
Verilog
32 lines
589 B
Verilog
// This should generate an error
|
|
|
|
module main;
|
|
|
|
reg[7:0] shared;
|
|
wire [7:0] not_shared = ~shared;
|
|
|
|
program test1;
|
|
initial shared <= 'h55;
|
|
endprogram :test1
|
|
|
|
program test2;
|
|
reg [7:0] tmp;
|
|
final begin
|
|
if (shared !== 'h55) begin
|
|
$display("FAILED -- shared=%b is not correct", shared);
|
|
$finish;
|
|
end
|
|
|
|
tmp <= ~shared; // ERROR: only blocking assign in final block
|
|
if (not_shared !== 'haa) begin
|
|
$display("FAILED -- not_shared is not correct", not_shared);
|
|
$finish;
|
|
end
|
|
|
|
$display("PASSED");
|
|
end
|
|
|
|
endprogram :test2
|
|
|
|
endmodule // main
|