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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
32 lines
643 B
Verilog
32 lines
643 B
Verilog
// This test program shows how programs can be contained by
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// modules, and can access variables in the context.
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module main;
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reg[7:0] shared;
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wire [7:0] not_shared = ~shared;
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program test1;
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initial shared <= 'h55;
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endprogram :test1
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program test2;
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reg [7:0] tmp;
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final begin
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if (shared !== 'h55) begin
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$display("FAILED -- shared=%b is not correct", shared);
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$finish;
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end
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tmp = ~shared;
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if (not_shared !== 'haa || not_shared !== tmp) begin
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$display("FAILED -- not_shared is not correct", not_shared);
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$finish;
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end
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$display("PASSED");
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end
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endprogram :test2
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endmodule // main
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