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By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
25 lines
490 B
Verilog
25 lines
490 B
Verilog
// This program block demonstrates that initial and final blocks
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// work, and that program variables work as well.
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program main;
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int foo;
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int bar;
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initial begin
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bar = 1;
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for (foo = 1 ; foo < 10 ; ++foo) begin
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bar = bar * foo;
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$display("foo = %d, bar=%d", foo, bar);
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end
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end
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final begin
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if (foo !== 10 || bar !== 362_880) begin
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$display("FAILED -- foo=%d", foo);
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end else begin
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$display("PASSED");
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end
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end
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endprogram // main
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