mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
145 lines
1.9 KiB
Verilog
145 lines
1.9 KiB
Verilog
`timescale 1ns / 1ps
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module top;
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reg sys_clk;
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reg sys_reset;
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integer cnt, lastcnt;
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initial begin
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sys_clk = 1'b1;
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sys_reset = 1'b1;
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cnt = 0;
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lastcnt = 100;
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while(cnt < lastcnt) begin
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#5;
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sys_clk = 1'b0;
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#5;
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sys_clk = 1'b1;
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if(cnt > 10) begin
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sys_reset = 1'b0;
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end
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cnt = cnt + 1;
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end
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#20;
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$dumpflush;
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$finish(2);
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$stop(2);
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end
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test1 #(
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.WIDTH1(18),
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.WIDTH2(18)
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) test1 (
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.sys_clk(sys_clk),
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.sys_rst(sys_reset)
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);
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test2 #(
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.WIDTH1(18),
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.WIDTH2(18)
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) test2_top (
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.sys_clk(sys_clk),
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.sys_rst(sys_reset)
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);
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endmodule
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module test1
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#(
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parameter WIDTH1 = 1,
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parameter WIDTH2 = 2
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) (
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input sys_clk,
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input sys_rst
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);
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wire [15:0] w1 = WIDTH1;
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wire [15:0] w2 = WIDTH2;
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generate
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if(WIDTH1 != 1) begin: not1
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test2 #(
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.WIDTH1(18),
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.WIDTH2(18)
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) test2_0 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst)
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);
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test2 #(
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.WIDTH1(18),
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.WIDTH2(18)
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) test2_1 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst)
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);
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end
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endgenerate
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initial begin
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#40;
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$finish(0);
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end
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endmodule
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module test2
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#(
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parameter WIDTH1 = 3,
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parameter WIDTH2 = 4
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) (
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input sys_clk,
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input sys_rst
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);
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localparam big_width = (WIDTH1 >= WIDTH2) ? WIDTH1 : WIDTH2;
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initial begin
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$display("%m big_width: %h", big_width);
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end
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wire [15:0] w1 = WIDTH1;
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wire [15:0] w2 = WIDTH2;
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wire [15:0] bigw = big_width;
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wire [31:0] out_data_a, out_data_b;
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test3 #(
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.WIDTH1(WIDTH1),
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.WIDTH2(WIDTH2)
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) test3_0 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst)
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);
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test3 test3_1 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst)
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);
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defparam test3_1.WIDTH1 = WIDTH1;
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defparam test3_1.WIDTH2 = WIDTH2;
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endmodule
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module test3 (sys_clk, sys_rst);
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input sys_clk;
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input sys_rst;
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parameter WIDTH1 = 0;
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parameter WIDTH2 = 0;
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localparam big_width = (WIDTH1 >= WIDTH2) ? WIDTH1 : WIDTH2;
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wire [31:0] wide = big_width;
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wire [31:0] width1 = WIDTH1;
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wire [31:0] width2 = WIDTH2;
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initial begin
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$strobe("%m wide: %h, width1:%h, width2:%h", wide, width1, width2);
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end
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endmodule
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