mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
111 lines
2.7 KiB
Verilog
111 lines
2.7 KiB
Verilog
/***********************************************************************
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*
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* Copyright (C) 2011 Adrian Wise
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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***********************************************************************
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*
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* This is a testbench exercising gate-level modelling of DTL gates,
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* distilled down (as a test-case) from a much larger design.
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* The gates can only pull down strongly to ground and have a weak
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* pull-up.
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*
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**********************************************************************/
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`timescale 1 ns / 100 ps
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module dtl_inv (op, in1);
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output op;
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input in1;
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not (strong0, pull1) #16 not1 (op, in1);
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endmodule // dtl_inv
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module sr_latch (p, n);
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inout p;
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inout n;
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dtl_inv u_p1
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( .in1 ( n ) ,
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.op ( p ) );
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dtl_inv u_n1
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( .in1 ( p ) ,
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.op ( n ) );
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endmodule // sr_latch
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module dut (pp, nn);
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inout [1:0] pp;
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inout [1:0] nn;
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sr_latch u_l1 (pp[0], nn[0]);
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endmodule // dut
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module top;
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reg pass;
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reg x;
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wire [1:0] pp;
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wire [1:0] nn;
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dtl_inv u_pp0(.in1(~x), .op(pp[0]));
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dtl_inv u_nn0(.in1( x), .op(nn[0]));
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dut u_d1 (pp, nn);
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initial begin
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pass = 1'b1;
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x <= 2'd0;
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#100;
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$display("Expect: x = 0, pp = z0, nn = z1 p=0, n=1");
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$display("Actual: x = %b, pp = %b, nn = %b p=%b, n=%b", x, pp, nn,
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u_d1.u_l1.p, u_d1.u_l1.n);
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if (x !== 1'b0) begin
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$display("Failed: expected x to be 0, got %b", x);
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pass = 1'b0;
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end
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if (pp !== 2'bz0) begin
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$display("Failed: expected pp to be z0, got %b", pp);
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pass = 1'b0;
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end
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if (nn !== 2'bz1) begin
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$display("Failed: expected nn to be z0, got %b", nn);
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pass = 1'b0;
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end
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if (u_d1.u_l1.p !== 1'b0) begin
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$display("Failed: expected p to be 0, got %b", u_d1.u_l1.p);
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pass = 1'b0;
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end
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if (u_d1.u_l1.n !== 1'b1) begin
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$display("Failed: expected n to be 1, got %b", u_d1.u_l1.n);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule // top
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