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https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
/*
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* Check that the initial value can be out of range and that the next()/prev()
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* enumeration methods do not change to a defined state.
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*/
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module top;
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reg pass;
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enum bit [3:0] {a2 = 1, b2 = 2, c2 = 3, d2 = 4} evar2;
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enum reg [3:0] {a4 = 1, b4 = 2, c4 = 3, d4 = 4} evar4;
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initial begin
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pass = 1'b1;
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if (evar2 !== 0) begin
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$display("Failed initial/2 value should be 0, got %d", evar2);
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pass = 1'b0;
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end
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if (evar4 !== 4'bx) begin
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$display("Failed initial/4 value should be 'bx, got %d", evar4);
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pass = 1'b0;
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end
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evar2 = evar2.next;
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if (evar2 !== 0) begin
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$display("Failed next/2 of an invalid value should be 0, got %d", evar2);
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pass = 1'b0;
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end
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evar4 = evar4.next;
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if (evar4 !== 4'bx) begin
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$display("Failed next/4 of an invalid value should be 0, got %d", evar4);
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pass = 1'b0;
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end
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evar2 = evar2.prev;
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if (evar2 !== 0) begin
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$display("Failed prev/2 of an invalid value should be 0, got %d", evar2);
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pass = 1'b0;
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end
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evar4 = evar4.prev;
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if (evar4 !== 4'bx) begin
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$display("Failed prev/4 of an invalid value should be 0, got %d", evar4);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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