mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-28 16:53:45 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
322 lines
8.0 KiB
Verilog
322 lines
8.0 KiB
Verilog
// Check the various variable bit selects (LSB > MSB).
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module top;
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parameter [-4:-1] ap = 4'h1;
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parameter [-4:-1] bp = 4'he;
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parameter [-3:0] cp = 4'h1;
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parameter [-3:0] dp = 4'he;
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reg passed;
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wire [-4:-1] a = 4'h1;
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wire [-4:-1] b = 4'he;
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wire [0:0] s0 = 0;
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wire [1:0] s1 = 0;
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wire [2:0] s2 = 0;
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reg [-4:-1] ar = 4'h1;
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reg [-4:-1] br = 4'he;
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wire [-3:0] c = 4'h1;
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wire [-3:0] d = 4'he;
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wire [0:0] s3 = 0;
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wire [1:0] s4 = 0;
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reg [-3:0] cr = 4'h1;
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reg [-3:0] dr = 4'he;
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wire res_a0 = a[s0];
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wire res_b0 = b[s0];
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wire res_a1 = a[s1];
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wire res_b1 = b[s1];
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wire res_a2 = a[s2];
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wire res_b2 = b[s2];
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wire res_c3 = c[s3];
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wire res_d3 = d[s3];
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wire res_c4 = c[s4];
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wire res_d4 = d[s4];
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reg [-4:-1] res_ab;
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reg [-3:0] res_cd;
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initial begin
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#1;
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passed = 1'b1;
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// Check procedural R-value variable bit selects of a net.
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$display("a[s0]: %b", a[s0]);
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if (a[s0] !== 1'bx) begin
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$display("Failed a[s0], expected 1'bx, got %b", a[s0]);
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passed = 1'b0;
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end
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$display("b[s0]: %b", b[s0]);
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if (b[s0] !== 1'bx) begin
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$display("Failed b[s0], expected 1'bx, got %b", b[s0]);
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passed = 1'b0;
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end
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$display("a[s1]: %b", a[s1]);
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if (a[s1] !== 1'bx) begin
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$display("Failed a[s1], expected 1'bx, got %b", a[s1]);
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passed = 1'b0;
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end
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$display("b[s1]: %b", b[s1]);
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if (b[s1] !== 1'bx) begin
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$display("Failed b[s1], expected 1'bx, got %b", b[s1]);
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passed = 1'b0;
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end
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$display("a[s2]: %b", a[s2]);
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if (a[s2] !== 1'bx) begin
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$display("Failed a[s2], expected 1'bx, got %b", a[s2]);
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passed = 1'b0;
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end
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$display("b[s2]: %b", b[s2]);
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if (b[s2] !== 1'bx) begin
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$display("Failed b[s2], expected 1'bx, got %b", b[s2]);
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passed = 1'b0;
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end
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$display("c[s3]: %b", c[s3]);
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if (c[s3] !== 1'b1) begin
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$display("Failed c[s3], expected 1'b1, got %b", c[s3]);
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passed = 1'b0;
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end
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$display("d[s3]: %b", d[s3]);
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if (d[s3] !== 1'b0) begin
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$display("Failed d[s3], expected 1'b0, got %b", d[s3]);
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passed = 1'b0;
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end
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$display("c[s4]: %b", c[s4]);
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if (c[s4] !== 1'b1) begin
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$display("Failed c[s4], expected 1'b1, got %b", c[s4]);
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passed = 1'b0;
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end
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$display("d[s4]: %b", d[s4]);
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if (d[s4] !== 1'b0) begin
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$display("Failed d[s4], expected 1'b0, got %b", d[s4]);
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passed = 1'b0;
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end
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// Check procedural R-value variable bit selects of a parameter.
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$display("ap[s0]: %b", ap[s0]);
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if (ap[s0] !== 1'bx) begin
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$display("Failed ap[s0], expected 1'bx, got %b", ap[s0]);
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passed = 1'b0;
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end
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$display("bp[s0]: %b", bp[s0]);
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if (bp[s0] !== 1'bx) begin
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$display("Failed bp[s0], expected 1'bx, got %b", bp[s0]);
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passed = 1'b0;
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end
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$display("ap[s1]: %b", ap[s1]);
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if (ap[s1] !== 1'bx) begin
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$display("Failed ap[s1], expected 1'bx, got %b", ap[s1]);
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passed = 1'b0;
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end
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$display("bp[s1]: %b", bp[s1]);
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if (bp[s1] !== 1'bx) begin
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$display("Failed bp[s1], expected 1'bx, got %b", bp[s1]);
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passed = 1'b0;
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end
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$display("ap[s2]: %b", ap[s2]);
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if (ap[s2] !== 1'bx) begin
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$display("Failed ap[s2], expected 1'bx, got %b", ap[s2]);
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passed = 1'b0;
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end
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$display("bp[s2]: %b", bp[s2]);
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if (bp[s2] !== 1'bx) begin
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$display("Failed bp[s2], expected 1'bx, got %b", bp[s2]);
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passed = 1'b0;
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end
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$display("cp[s3]: %b", cp[s3]);
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if (cp[s3] !== 1'b1) begin
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$display("Failed cp[s3], expected 1'b1, got %b", cp[s3]);
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passed = 1'b0;
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end
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$display("dp[s3]: %b", dp[s3]);
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if (dp[s3] !== 1'b0) begin
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$display("Failed dp[s3], expected 1'b0, got %b", dp[s3]);
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passed = 1'b0;
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end
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$display("cp[s4]: %b", cp[s4]);
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if (cp[s4] !== 1'b1) begin
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$display("Failed cp[s4], expected 1'b1, got %b", cp[s4]);
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passed = 1'b0;
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end
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$display("dp[s4]: %b", dp[s4]);
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if (dp[s4] !== 1'b0) begin
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$display("Failed dp[s4], expected 1'b0, got %b", dp[s4]);
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passed = 1'b0;
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end
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// Check procedural R-value variable bit selects of a reg.
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$display("ar[s0]: %b", ar[s0]);
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if (ar[s0] !== 1'bx) begin
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$display("Failed ar[s0], expected 1'bx, got %b", ar[s0]);
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passed = 1'b0;
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end
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$display("br[s0]: %b", br[s0]);
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if (br[s0] !== 1'bx) begin
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$display("Failed br[s0], expected 1'bx, got %b", br[s0]);
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passed = 1'b0;
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end
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$display("ar[s1]: %b", ar[s1]);
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if (ar[s1] !== 1'bx) begin
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$display("Failed ar[s1], expected 1'bx, got %b", ar[s1]);
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passed = 1'b0;
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end
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$display("br[s1]: %b", br[s1]);
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if (br[s1] !== 1'bx) begin
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$display("Failed br[s1], expected 1'bx, got %b", br[s1]);
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passed = 1'b0;
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end
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$display("ar[s2]: %b", ar[s2]);
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if (ar[s2] !== 1'bx) begin
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$display("Failed ar[s2], expected 1'bx, got %b", ar[s2]);
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passed = 1'b0;
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end
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$display("br[s2]: %b", br[s2]);
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if (br[s2] !== 1'bx) begin
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$display("Failed br[s2], expected 1'bx, got %b", br[s2]);
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passed = 1'b0;
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end
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$display("cr[s3]: %b", cr[s3]);
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if (cr[s3] !== 1'b1) begin
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$display("Failed cr[s3], expected 1'b1, got %b", cr[s3]);
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passed = 1'b0;
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end
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$display("dr[s3]: %b", dr[s3]);
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if (dr[s3] !== 1'b0) begin
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$display("Failed dr[s3], expected 1'b0, got %b", dr[s3]);
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passed = 1'b0;
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end
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$display("cr[s4]: %b", cr[s4]);
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if (cr[s4] !== 1'b1) begin
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$display("Failed cr[s4], expected 1'b1, got %b", cr[s4]);
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passed = 1'b0;
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end
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$display("dr[s4]: %b", dr[s4]);
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if (dr[s4] !== 1'b0) begin
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$display("Failed dr[s4], expected 1'b0, got %b", dr[s4]);
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passed = 1'b0;
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end
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// Check continuous assignment R-value variable bit selects.
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if (res_a0 !== 1'bx) begin
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$display("Failed res_a0, expected 1'bx, got %b", res_a0);
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passed = 1'b0;
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end
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if (res_b0 !== 1'bx) begin
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$display("Failed res_b0, expected 1'bx, got %b", res_b0);
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passed = 1'b0;
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end
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if (res_a1 !== 1'bx) begin
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$display("Failed res_a1, expected 1'bx, got %b", res_a1);
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passed = 1'b0;
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end
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if (res_b1 !== 1'bx) begin
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$display("Failed res_b1, expected 1'bx, got %b", res_b1);
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passed = 1'b0;
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end
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if (res_a2 !== 1'bx) begin
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$display("Failed res_a2, expected 1'bx, got %b", res_a2);
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passed = 1'b0;
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end
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if (res_b2 !== 1'bx) begin
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$display("Failed res_b2, expected 1'bx, got %b", res_b2);
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passed = 1'b0;
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end
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if (res_c3 !== 1'b1) begin
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$display("Failed res_c3, expected 1'b1, got %b", res_c3);
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passed = 1'b0;
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end
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if (res_d3 !== 1'b0) begin
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$display("Failed res_d3, expected 1'b0, got %b", res_d3);
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passed = 1'b0;
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end
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if (res_c4 !== 1'b1) begin
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$display("Failed res_c4, expected 1'b1, got %b", res_c4);
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passed = 1'b0;
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end
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if (res_d4 !== 1'b0) begin
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$display("Failed res_d4, expected 1'b0, got %b", res_d4);
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passed = 1'b0;
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end
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// Check procedural L-value variable bit selects.
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res_ab = 4'bxxxx;
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res_ab[s0] = 1'b0;
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if (res_ab !== 4'bxxxx) begin
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$display("Failed res_ab[s0], expected 4'bxxxx, got %b", res_ab);
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passed = 1'b0;
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end
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res_ab = 4'bxxxx;
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res_ab[s1] = 1'b0;
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if (res_ab !== 4'bxxxx) begin
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$display("Failed res_ab[s1], expected 4'bxxxx, got %b", res_ab);
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passed = 1'b0;
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end
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res_ab = 4'bxxxx;
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res_ab[s2] = 1'b0;
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if (res_ab !== 4'bxxxx) begin
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$display("Failed res_ab[s2], expected 4'bxxxx, got %b", res_ab);
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passed = 1'b0;
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end
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res_cd = 4'bxxxx;
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res_cd[s3] = 1'b0;
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if (res_cd !== 4'bxxx0) begin
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$display("Failed res_cd[s3], expected 4'bxxx0, got %b", res_cd);
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passed = 1'b0;
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end
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res_cd = 4'bxxxx;
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res_cd[s4] = 1'b0;
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if (res_cd !== 4'bxxx0) begin
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$display("Failed res_cd[s4], expected 4'bxxx0, got %b", res_cd);
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passed = 1'b0;
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end
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if (passed) $display("Compare tests passed");
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end
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endmodule
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