mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
43 lines
883 B
Verilog
43 lines
883 B
Verilog
module main;
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reg pass;
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genvar i;
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generate
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for( i=1; i<3; i=i+1 )
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begin : U
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reg [1:0] x;
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end
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for( i=0; i<2; i=i+1 )
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begin : V
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initial begin
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U[(i+1)%4].x = 2'd0;
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#5;
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U[(i+1)%4].x = i;
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end
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end
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endgenerate
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initial begin
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pass = 1'b1;
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#4;
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if (U[1].x != 2'd0) begin
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$display("Failed to clear U[1].x, got %b", U[1].x);
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pass = 1'b0;
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end
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if (U[2].x != 2'd0) begin
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$display("Failed to clear U[2].x, got %b", U[1].x);
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pass = 1'b0;
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end
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#2;
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if (U[1].x != 2'd0) begin
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$display("Failed to set U[1].x, expected 2'd0, got %b", U[1].x);
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pass = 1'b0;
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end
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if (U[2].x != 2'd1) begin
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$display("Failed to set U[2].x, expected 2'd1, got %b", U[1].x);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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