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https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
30 lines
847 B
Verilog
30 lines
847 B
Verilog
module top;
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lower #(1, 2, 3) dut();
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endmodule
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module lower;
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parameter one = 1; // This should be 'sd1
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parameter two = 2; // This should be 'sd2
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parameter three = 0; // This should be 'sd3
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parameter local1 = one - two; // This should be -'sd1
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parameter local_t1 = local1 * 1; // This should be -'d1
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parameter local_d1 = local1 / 1; // This should be -'d1
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reg err;
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initial begin
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err = 0;
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if (local_t1 !== -1) err = 1;
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if (local_t1 > 0) err = 1;
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if (local_d1 !== -1) err = 1;
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if (local_d1 > 0) err = 1;
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if (! $is_signed(local_t1)) err = 1;
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if (! $is_signed(local_d1)) err = 1;
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if (! $is_signed(local1)) err = 1;
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if (err == 0) $display("PASSED");
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else $display("FAILED");
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end
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endmodule
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