mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
63 lines
1.4 KiB
Verilog
63 lines
1.4 KiB
Verilog
`ifdef __ICARUS__
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`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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`endif
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module top;
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reg pass;
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reg [5:0] cond;
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reg [2:1] expr;
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integer result;
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always @(cond or expr) begin
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casex (cond)
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6'b01_??10 : result = 1;
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{2'b10, 4'b??10} : result = 2;
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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{expr[1:0], 4'b??01} : result = 3;
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expr[11:6] : result = 4;
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`else
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{expr[1], 1'bx, 4'b??01} : result = 3;
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6'bxxxxxx : result = 4;
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`endif
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default : result = 0;
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endcase
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end
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initial begin
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pass = 1'b1;
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expr = 2'b10;
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cond = 6'b01_xx10;
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#1 if (result != 1) begin
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$display("Failed case expr 1 test, got expr %0d", result);
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pass = 1'b0;
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end
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cond = 6'bxx_xxxx;
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#1 if (result != 1) begin
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$display("Failed case expr 1a test, got expr %0d", result);
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pass = 1'b0;
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end
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cond = 6'b10_zz10;
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#1 if (result != 2) begin
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$display("Failed case expr 2 test, got expr %0d", result);
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pass = 1'b0;
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end
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cond = 6'b0x_zz01;
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#1 if (result != 3) begin
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$display("Failed case expr 3 test, got expr %0d", result);
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pass = 1'b0;
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end
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cond = 6'b11_1111;
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#1 if (result != 4) begin
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$display("Failed case expr 1a test, got expr %0d", result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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