mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
80 lines
2.4 KiB
Verilog
80 lines
2.4 KiB
Verilog
`ifdef __ICARUS__
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`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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`endif
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module top;
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reg pass = 1'b1;
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wire [3:0] part_idx_up, part_idx_down, part_sel;
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wire [3:0] ps_array [1:0];
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// Check the positive indexed part select.
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// assign part_idx_up[-1+:2] = 2'b01; // We do not currently support this!
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assign part_idx_up[1+:2] = 2'b01;
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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assign part_idx_up[3+:2] = 2'b01;
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assign part_idx_up[5+:2] = 2'b01; // This should be skipped
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assign part_idx_up[7+:3] = 3'b001; // This should be skipped
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`else
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assign part_idx_up[3] = 1'b1;
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`endif
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// Check the negative indexed part select.
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// assign part_idx_down[0-:2] = 2'b10; // We do not currently support this!
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assign part_idx_down[2-:2] = 2'b10;
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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assign part_idx_down[4-:2] = 2'b10;
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assign part_idx_down[6-:2] = 2'b10; // This should be skipped
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assign part_idx_down[9-:3] = 3'b100; // This should be skipped
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`else
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assign part_idx_down[3] = 1'b0;
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`endif
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// Check a normal constant part select.
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// assign part_sel[1:-1] = 2'b01; // We do not currently support this!
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assign part_sel[2:1] = 2'b01;
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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assign part_sel[4:3] = 2'b01;
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assign part_sel[6:5] = 2'b01; // This should be skipped
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assign part_sel[9:7] = 3'b001; // This should be skipped
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`else
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assign part_sel[3] = 1'b1;
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`endif
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// Check a normal constant part select on an array.
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// assign ps_array[0][1:-1] = 2'b01; // We do not currently support this!
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assign ps_array[0][2:1] = 2'b01;
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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assign ps_array[0][4:3] = 2'b01;
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assign ps_array[0][6:5] = 2'b01; // This should be skipped
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assign ps_array[0][9:7] = 3'b001; // This should be skipped
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`else
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assign ps_array[0][3] = 1'b1;
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`endif
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initial begin
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#1;
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if (part_idx_up !== 4'b101z) begin
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$display("Failed +: select, expected 4'b101z, got %b", part_idx_up);
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pass = 1'b0;
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end
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if (part_idx_down !== 4'b010z) begin
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$display("Failed -: select, expected 4'b010z, got %b", part_idx_down);
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pass = 1'b0;
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end
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if (part_sel !== 4'b101z) begin
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$display("Failed const. part select, expected 4'b101z, got %b", part_sel);
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pass = 1'b0;
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end
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if (ps_array[0] !== 4'b101z) begin
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$display("Failed array part select, expected 4'b101z, got %b",
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ps_array[0]);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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