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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
61 lines
1.3 KiB
Verilog
61 lines
1.3 KiB
Verilog
module top;
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integer chr, fd, code;
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reg [14*8:1] str;
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initial begin
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// Put a string into the file.
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fd = $fopen("work/test.txt", "w");
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if (fd == 0) begin
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$display("Failed to open test file for writing!");
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$finish;
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end
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$fdisplay(fd, "Hello World!");
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$fclose(fd);
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// Now read it back and verify that $ungetc() and other things work.
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fd = $fopen("work/test.txt", "r");
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if (fd == 0) begin
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$display("Failed to open test file for reading!");
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$finish;
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end
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chr = $fgetc(fd);
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if (chr != "H") begin
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$display("Failed first character read!");
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$finish;
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end
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code = $ungetc(chr, fd);
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if (code == -1) begin
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$display("Failed to ungetc() character!");
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$finish;
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end
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chr = $fgetc(fd);
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if (chr != "H") begin
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$display("Failed first character reread!");
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$finish;
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end
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code = $ungetc(chr, fd);
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if (code == -1) begin
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$display("Failed to ungetc() character (2)!");
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$finish;
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end
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code = $fgets(str, fd);
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if (code == 0) begin
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$display("Failed to read characters!");
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$finish;
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end
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if (str[13*8:9] != "Hello World!") begin
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$display("Read wrong characters!");
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$finish;
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end
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$fclose(fd);
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$display("PASSED");
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end
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endmodule
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