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https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
38 lines
1010 B
Verilog
38 lines
1010 B
Verilog
module top;
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reg pass = 1'b1;
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reg [1:0] rval = 2'b10;
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wire [1:0] wval = (wval > 0) ? 2'b01 : 2'b00;
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// This works as follows:
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// rlval starts are 0.0 which is not greater than 0.0 (false).
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// This sets rlval to 2.0 which is greater than 0.0 (true).
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// This then sets the value to 1.0 which is still true and stable.
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wire real rlval = (rlval > 0.0) ? 1.0 : 2.0;
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initial begin
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#1;
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if (rval != 2'b10) begin
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$display("FAILED initial value expected 2'b10, got %b.", rval);
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pass = 1'b0;
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end
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if (wval !== 2'b0x) begin
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$display("FAILED net value expected 2'b0x, got %b.", wval);
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pass = 1'b0;
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end
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if (rlval != 1.0) begin
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$display("FAILED net real value expected 1.0, got %f.", rlval);
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pass = 1'b0;
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end
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#1 assign rval = (rval > 0) ? 2'b01 : 2'b00;
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if (rval != 2'b01) begin
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$display("FAILED forced value expected 2'b01, got %b.", rval);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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