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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
32 lines
491 B
Verilog
32 lines
491 B
Verilog
module top;
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wire net1, net2;
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reg [1:0] data;
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buf bus_drv[1:0] (net1, net2, data);
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initial begin
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data = 0;
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#1 $monitor(net1,,net2,,data);
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#1 if (net1 !== 1'b0) begin
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$display("FAILED");
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$finish;
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end
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data = 3;
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#1 if (net1 !== 1'b1) begin
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$display("FAILED");
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$finish;
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end
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data = 1;
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#1 if (net1 !== 1'bx) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule
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