Files
iverilog/ivtest/ivltests/parameter_scalar.v
T
Lars-Peter Clausen 37392383b5 Add regression test for scalar and 1-bit parameters
Check that scalar typed parameters are handled correctly. Make sure the
width of the parameter only depends on the type and not on the value
assigned to the parameter.

Same for parameters with a 1-bit range specification.

Signed-off-by: Lars-Peter Clausen <[email protected]>
2022-05-02 14:33:31 +02:00

27 lines
507 B
Verilog

// Check that parameters with a scalar type are handled correctly
module test #(
// This should get truncated to 1'b1
parameter bit P = 2'b11
);
bit failed = 1'b0;
`define check(expr, val) \
if (expr !== val) begin \
$display("FAILED: `%s`, expected %0d, got %0d", `"expr`", val, expr); \
failed = 1'b1; \
end
initial begin
`check($bits(P), 1);
`check(P + 1'b1, 1'b0);
`check(P, 1'b1);
if (!failed) begin
$display("PASSED");
end
end
endmodule