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Lars-Peter Clausen
91579c7c79
SystemVerilog supports parameters without default values in parameter port list. Add regression tests to check this feature. Also add a regression test to check that modules without a default parameter are not automatically picked as a toplevel module. Signed-off-by: Lars-Peter Clausen <[email protected]>
15 lines
251 B
Verilog
15 lines
251 B
Verilog
// Check that modules with undefined parameters do not get picked as top-level
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// modules.
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module a #(
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parameter A
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);
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initial $display("FAILED");
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endmodule
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module b #(
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parameter B = 1
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);
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initial $display("PASSED");
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endmodule
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