mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-28 16:53:45 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
72 lines
1.9 KiB
Verilog
72 lines
1.9 KiB
Verilog
module top;
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reg pass = 1'b1;
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integer delay;
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reg [3:0] in = 4'h0;
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reg [7:0] result [1:0];
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initial begin
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result[0] <= #10 8'h00;
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if ($simtime != 0 || result[0] !== 8'bx) begin
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$display("Failed #10 blocked at %0t, expected 8'hxx, got %h",
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$simtime, result[0]);
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pass = 1'b0;
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end
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@(result[0]);
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if ($simtime != 10 || result[0] !== 8'h00) begin
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$display("Failed #10 at %0t, expected 8'h00, got %h",
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$simtime, result[0]);
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pass = 1'b0;
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end
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result[0][8:5] <= #10 4'hb;
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@(result[0]);
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if ($simtime != 20 || result[0] !== 8'h60) begin
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$display("Failed MSB #10 at %0t, expected 8'h60, got %h",
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$simtime, result[0]);
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pass = 1'b0;
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end
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result[0][1:-2] <= #10 4'hb;
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@(result[0]);
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if ($simtime != 30 || result[0] !== 8'h62) begin
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$display("Failed LSB #10 at %0t, expected 8'h62, got %h",
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$simtime, result[0]);
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pass = 1'b0;
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end
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delay = 20;
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result[1] <= #delay 8'h00;
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if ($simtime != 30 || result[1] !== 8'bx) begin
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$display("Failed #delay blocked at %0t, expected 8'hxx, got %h",
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$simtime, result[1]);
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pass = 1'b0;
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end
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@(result[1]);
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if ($simtime != 50 || result[1] !== 8'h00) begin
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$display("Failed #delay at %0t, expected 8'h00, got %h",
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$simtime, result[1]);
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pass = 1'b0;
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end
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result[1][8:5] <= #delay 4'hb;
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@(result[1]);
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if ($simtime != 70 || result[1] !== 8'h60) begin
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$display("Failed MSB #delay at %0t, expected 8'h60, got %h",
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$simtime, result[1]);
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pass = 1'b0;
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end
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result[1][1:-2] <= #delay 4'hb;
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@(result[1]);
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if ($simtime != 90 || result[1] !== 8'h62) begin
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$display("Failed LSB #delay at %0t, expected 8'h62, got %h",
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$simtime, result[1]);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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$finish;
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end
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endmodule
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