mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
39 lines
916 B
Verilog
39 lines
916 B
Verilog
`timescale 1us/100ns
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module top;
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reg pass = 1;
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reg [3:0] ia = 4'd1, ib = 4'd2;
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wire [2:0] icon, irep;
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/* Integer concatenation. */
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assign #1 icon = {ib[1:0], ia[0]}; // 5
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/* Integer replication. */
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assign #1 irep = {3{ia[0]}}; // 7
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initial begin
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#0.9;
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if (icon !== 3'bx) begin
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pass = 1'b0;
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$display("Failed: concatenation is not delayed, expected 3'bx got %b.", icon);
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end
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if (irep !== 3'bx) begin
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pass = 1'b0;
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$display("Failed: replication is not delayed, expected 3'bx got %b.", irep);
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end
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#0.1;
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#0;
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if (icon !== 3'd5) begin
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pass = 1'b0;
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$display("Failed: concatenation has incorrect value, expected 3'd5 got %b.", icon);
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end
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if (irep !== 3'd7) begin
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pass = 1'b0;
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$display("Failed: replication has incorrect value, expected 3'd7 got %b.", irep);
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end
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if (pass) $display("PASSED");
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end
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endmodule
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