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Lars-Peter Clausen
f53a95840a
Check that a output port that has a explicit data type, but no explicit net type is elaborated as a variable type port. Signed-off-by: Lars-Peter Clausen <[email protected]>
21 lines
327 B
Verilog
21 lines
327 B
Verilog
// Check that non-ANSI output ports that have a Verilog data type are elaborated
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// as variables and be assigned a value.
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module test;
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output reg a;
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output reg [1:0] b;
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output reg signed [1:0] c;
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output integer d;
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output time e;
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initial begin
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a = 0;
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b = 0;
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c = 0;
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d = 0;
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e = 0;
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$display("PASSED");
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end
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endmodule
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