mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
81 lines
2.2 KiB
Verilog
81 lines
2.2 KiB
Verilog
`begin_keywords "1364-2005"
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module generate_multi_loop();
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reg [31:0] input_value;
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wire [31:0] output_value;
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generate
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genvar i;
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genvar j;
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for (i = 0; i < 4; i = i + 1) begin:byte
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wire [7:0] byte_value;
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for (j = 0; j < 8; j = j + 1) begin:bit
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wire bit_value;
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buf buffer(bit_value, input_value[i*8+j]);
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assign byte_value[j] = bit_value;
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end
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assign output_value[i*8+7:i*8] = byte_value;
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end
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endgenerate
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initial begin
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input_value = 32'h12345678;
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#1;
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$write("byte_value =");
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$write(" %b", byte[3].byte_value);
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$write(" %b", byte[2].byte_value);
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$write(" %b", byte[1].byte_value);
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$write(" %b", byte[0].byte_value);
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$write("\n");
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$write("bit_value = ");
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$write("%b", byte[3].bit[7].bit_value);
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$write("%b", byte[3].bit[6].bit_value);
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$write("%b", byte[3].bit[5].bit_value);
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$write("%b", byte[3].bit[4].bit_value);
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$write("%b", byte[3].bit[3].bit_value);
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$write("%b", byte[3].bit[2].bit_value);
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$write("%b", byte[3].bit[1].bit_value);
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$write("%b", byte[3].bit[0].bit_value);
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$write(" ");
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$write("%b", byte[2].bit[7].bit_value);
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$write("%b", byte[2].bit[6].bit_value);
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$write("%b", byte[2].bit[5].bit_value);
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$write("%b", byte[2].bit[4].bit_value);
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$write("%b", byte[2].bit[3].bit_value);
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$write("%b", byte[2].bit[2].bit_value);
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$write("%b", byte[2].bit[1].bit_value);
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$write("%b", byte[2].bit[0].bit_value);
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$write(" ");
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$write("%b", byte[1].bit[7].bit_value);
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$write("%b", byte[1].bit[6].bit_value);
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$write("%b", byte[1].bit[5].bit_value);
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$write("%b", byte[1].bit[4].bit_value);
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$write("%b", byte[1].bit[3].bit_value);
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$write("%b", byte[1].bit[2].bit_value);
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$write("%b", byte[1].bit[1].bit_value);
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$write("%b", byte[1].bit[0].bit_value);
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$write(" ");
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$write("%b", byte[0].bit[7].bit_value);
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$write("%b", byte[0].bit[6].bit_value);
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$write("%b", byte[0].bit[5].bit_value);
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$write("%b", byte[0].bit[4].bit_value);
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$write("%b", byte[0].bit[3].bit_value);
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$write("%b", byte[0].bit[2].bit_value);
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$write("%b", byte[0].bit[1].bit_value);
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$write("%b", byte[0].bit[0].bit_value);
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$write("\n");
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if (output_value == input_value)
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$display("Test passed");
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else
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$display("Test FAILED");
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end
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endmodule
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`end_keywords
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