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https://github.com/steveicarus/iverilog.git
synced 2026-08-28 16:53:45 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
29 lines
704 B
Verilog
29 lines
704 B
Verilog
module test;
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parameter BYTES = 2;
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localparam mxbit = BYTES*8-1;
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function integer clog2;
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input value;
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integer value;
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for (clog2=0; value>0; clog2=clog2+1) value = value >> 1;
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endfunction
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// This is not recognized as a constant function call!
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localparam cntrw = clog2(mxbit);
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integer tmp;
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initial begin
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tmp = mxbit;
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$display("The maximum bit is %0d and uses a %0d bit counter", mxbit, cntrw);
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$display("clog2 does works here! Got %0d, should be %0d.", clog2(mxbit), clog2(tmp));
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if (cntrw !== clog2(tmp)) begin
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$display("FAILED -- cntrw=%0d", cntrw);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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