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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
63 lines
1.6 KiB
Verilog
63 lines
1.6 KiB
Verilog
module test;
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reg fail = 1'b0;
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reg [3:0] in = 4'b0;
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wire [3:0] bus;
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wire [3:0] val;
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assign (pull1, pull0) bus = in;
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assign val = bus;
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initial begin
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// Check the initial value.
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#1 if (val !== 4'b0) begin
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$display("FAILED: initial value, got %b, expected 0000.", val);
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fail = 1'b1;
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end
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// Check a bit force and verify a normal bit assign does nothing.
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#1 force bus[0] = 1'b1;
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#1 in[0] = 1'bz;
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#1 if (val !== 4'b0001) begin
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$display("FAILED: force of bus[0], got %b, expected 0001.", val);
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fail = 1'b1;
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end
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// Check a part force.
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#1 force bus[3:2] = 2'b11;
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#1 if (val !== 4'b1101) begin
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$display("FAILED: force of bus[3:2], got %b, expected 1101.", val);
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fail = 1'b1;
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end
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// Check that we can change an unforced bit.
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#1 in[1] = 1'bz;
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#1 if (val !== 4'b11z1) begin
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$display("FAILED: assignment of bus[1], got %b, expected 11z1.", val);
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fail = 1'b1;
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end
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#1 in[1] = 1'b0;
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// Check a bit release.
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#1 release bus[0];
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#1 if (val !== 4'b110z) begin
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$display("FAILED: release of bus[0], got %b, expected 110z.", val);
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fail = 1'b1;
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end
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// Check a part release.
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#1 release bus[3:2];
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#1 if (val !== 4'b000z) begin
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$display("FAILED: release of bus[3:2], got %b, expected 000z.", val);
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fail = 1'b1;
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end
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// Check a force from the upper thread bits (>= 8).
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#1 force bus[2:1] = 2'bx1;
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#1 if (val !== 4'b0x1z) begin
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$display("FAILED: force of bus[2:1], got %b, expected 0x1z.", val);
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fail = 1'b1;
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end
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if (!fail) $display("PASSED");
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end
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endmodule
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