mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-28 16:53:45 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
55 lines
997 B
Verilog
55 lines
997 B
Verilog
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module test
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#(parameter inputs = 8)
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(output reg [inputs-1:0] Q,
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input wire [inputs-1:0] D,
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input wire [inputs-1:0] I);
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// This should synthesize to an unrolled version of the
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// for loop.
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integer j;
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always @* begin
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for (j = 0 ; j < inputs ; j += 1) begin
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if (I[j]) Q[j] = ~D[j];
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else Q[j] = D[j];
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end
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end
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endmodule // test
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module main;
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wire [7:0] Q;
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reg [7:0] D, I;
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test dut (.Q(Q), .D(D), .I(I));
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(* ivl_synthesis_off *)
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initial begin
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D = 0;
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I = 0;
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#1 if (Q !== 8'h00) begin
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$display("FAILED -- Q=%h, D=%h, I=%h", Q, D, I);
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$finish;
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end
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D = 'h55;
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I = 'h55;
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#1 if (Q !== 8'h00) begin
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$display("FAILED -- Q=%h, D=%h, I=%h", Q, D, I);
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$finish;
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end
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D = 'h55;
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I = 'haa;
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#1 if (Q !== 8'hff) begin
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$display("FAILED -- Q=%h, D=%h, I=%h", Q, D, I);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // main
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