mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
71 lines
1.7 KiB
Verilog
71 lines
1.7 KiB
Verilog
// Copyright (c) 2015 CERN
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// Maciej Suminski <[email protected]>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Tests enum as a port type.
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typedef enum integer { var_presence, var_identif, var_1, var_2, var_3, var_rst, var_4, var_5, var_whatever } t_var;
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module enum_ports(input wire t_var var_i, output t_var var_o, output reg is_var_rst);
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initial begin
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var_o = var_presence;
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end
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always @(var_i)
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begin
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if(var_i == var_rst)
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is_var_rst = 1'b1;
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else
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is_var_rst = 1'b0;
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end
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endmodule
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module test_unit();
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t_var var_in, var_out;
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reg result;
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enum_ports dut(var_in, var_out, result);
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initial begin
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#1;
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if(var_out !== var_presence) begin
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$display("FAILED 1");
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$finish();
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end
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var_in = var_1;
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#1;
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if(result !== 1'b0) begin
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$display("FAILED 2");
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$finish();
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end
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var_in = var_rst;
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#1
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if(result !== 1'b1) begin
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$display("FAILED 3");
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$finish();
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end
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$display("PASSED");
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end
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endmodule
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