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https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
51 lines
784 B
Verilog
51 lines
784 B
Verilog
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module DFF
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(output reg Q,
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input wire D,
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input wire CLK,
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input wire RST
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/* */);
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always @(posedge CLK or posedge RST)
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if (RST)
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Q <= 0;
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else
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Q <= D;
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endmodule // dut
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module main;
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wire q;
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reg d, clk, rst;
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DFF dut (.Q(q), .D(d), .CLK(clk), .RST(rst));
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initial begin
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clk <= 1;
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d <= 1;
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#1 rst <= 1;
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#1 if (q !== 1'b0) begin
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$display("FAILED -- RST=%b, Q=%b", rst, q);
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$finish;
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end
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#1 rst <= 0;
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#1 if (q !== 1'b0) begin
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$display("FAILED -- RST=%b, Q=%b", rst, q);
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$finish;
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end
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#1 clk <= 0;
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#1 clk <= 1;
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#1 if (q !== d) begin
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$display("FAILED -- Q=%b, D=%b", q, d);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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