mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-28 16:53:45 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
60 lines
1.3 KiB
Verilog
60 lines
1.3 KiB
Verilog
module main;
|
|
|
|
reg [7:0] period;
|
|
|
|
reg drive;
|
|
wire trace;
|
|
|
|
// This is the main point of the test. Non-constant delay expressions
|
|
// should work here.
|
|
assign #(period/3) trace = drive;
|
|
|
|
initial begin
|
|
period = 8*3;
|
|
// Initially, set up a period=8 and get the trace to start
|
|
// following the drive.
|
|
#1 drive <= 1;
|
|
#9 if (trace !== drive) begin
|
|
$display("FAILED -- time=%0t, drive=%b, trace=%b",
|
|
$time, drive, trace);
|
|
$finish;
|
|
end
|
|
|
|
// The drive should NOT change the trace before the period.
|
|
drive <= 0;
|
|
|
|
#7 if (trace !== 1'b1) begin
|
|
$display("FAILED -- time=%0t, drive=%b, trace=%b",
|
|
$time, drive, trace);
|
|
$finish;
|
|
end
|
|
#2 if (trace !== drive) begin
|
|
$display("FAILED -- time=%0t, drive=%b, trace=%b",
|
|
$time, drive, trace);
|
|
$finish;
|
|
end
|
|
|
|
// Change the period.
|
|
period = 6*3;
|
|
|
|
// Now check that the new delay is taken.
|
|
#1 drive <= 1;
|
|
|
|
#5 if (trace !== 1'b0) begin
|
|
$display("FAILED -- time=%0t, drive=%b, trace=%b",
|
|
$time, drive, trace);
|
|
$finish;
|
|
end
|
|
|
|
#2 if (trace !== drive) begin
|
|
$display("FAILED -- time=%0t, drive=%b, trace=%b",
|
|
$time, drive, trace);
|
|
$finish;
|
|
end
|
|
|
|
$display("PASSED");
|
|
$finish;
|
|
end
|
|
|
|
endmodule // main
|