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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
43 lines
1.2 KiB
Verilog
43 lines
1.2 KiB
Verilog
/* dcomp1.v - this is a fragment of a larger program, which would
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* dynamicly compute a more interesting value for the phdelay variable.
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*
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* It illustrates a problem in verilog-20010721 when computing
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* time values for use in behavioral delays.
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*/
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`timescale 1ps / 1ps
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module dcomp;
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time phdelay;
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parameter clk_period = 400;
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parameter phoffset = 4;
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time compdelay;
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reg internal_Clk, Clk;
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initial begin
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$monitor("%b %b %t %t %t", internal_Clk, Clk, phdelay, compdelay, $time);
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phdelay = 0;
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#2000;
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phdelay = 13;
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#2001;
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$finish(0);
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end // initial begin
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initial internal_Clk <= 0;
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always #(clk_period/2) internal_Clk = ~internal_Clk;
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always @(internal_Clk) begin
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// uncoment only one of the next four lines:
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// #(phdelay); // works
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// #(phdelay + phoffset); // fails
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compdelay = phdelay + phoffset; #(compdelay); // fails
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// compdelay = phdelay + 4; #(compdelay); // fails
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$display("got here");
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Clk <= internal_Clk;
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// of course, this is what I really want... (but that's PR#105)
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// Clk <= #(phdelay + phoffset + clk_period/2) internal_Clk;
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end // always @ (internal_Clk)
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endmodule // dcomp
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