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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
58 lines
1.1 KiB
Verilog
58 lines
1.1 KiB
Verilog
`begin_keywords "1364-2005"
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/*
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* This tests the synthesis of a case statement that has an empty case.
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*/
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module main;
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reg clk, bit, foo;
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// Synchronous device that toggles whenever enabled by a high bit.
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always @(posedge clk)
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case (bit)
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1'b0: ;
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1'b1: foo <= ~foo;
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endcase // case(bit)
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(* ivl_synthesis_off *)
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always begin
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#5 clk = 1;
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#5 clk = 0;
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end
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(* ivl_synthesis_off *)
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initial begin
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clk = 0;
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bit = 0;
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foo = 0;
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# 6 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
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if (bit !== 0 || foo !== 0) begin
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$display("FAILED");
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$finish;
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end
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#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
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if (bit !== 0 || foo !== 0) begin
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$display("FAILED");
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$finish;
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end
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bit <= 1;
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#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
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if (bit !== 1 || foo !== 1) begin
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$display("FAILED");
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$finish;
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end
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#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
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if (bit !== 1 || foo !== 0) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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`end_keywords
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