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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
20 lines
338 B
Verilog
20 lines
338 B
Verilog
module test();
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wire [7:0] value1;
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wire bit [7:0] value2;
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assign value1[3:0] = 4'd2;
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assign value2 = value1;
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initial begin
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// value1 gets cast to 2-state, so 'z' bits are converted to '0'.
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#2 $display("%b %b", value1, value2);
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if (value2 === 8'b00000010)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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