mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
42 lines
573 B
Verilog
42 lines
573 B
Verilog
`ifdef __ICARUS__
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`define SUPPORT_TWO_STATE_NETS_IN_IVTEST
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`endif
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module test();
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int x2;
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int z2;
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function int y2(int x);
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endfunction
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`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
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wire int w2 = y2(x2);
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`else
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wire integer w2 = 0;
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`endif
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integer x4;
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integer z4;
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function integer y4(integer x);
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endfunction
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wire integer w4 = y4(x4);
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initial begin
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#1;
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$display(w2);
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z2 = y2(x2);
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$display(z2);
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$display(w4);
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z4 = y4(x4);
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$display(z4);
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if (w2 === 0 && z2 === 0 && w4 === 'bx && z4 === 'bx)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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