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https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
31 lines
521 B
Verilog
31 lines
521 B
Verilog
module bar(clk, rst, inp, out);
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(* this_is_clock = 1 *)
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input wire clk;
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(* this_is_reset = 1 *)
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input wire rst;
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input wire inp;
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(* an_output_register = 1*)
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output reg out;
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always @(posedge clk)
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if (rst) out <= 1'd0;
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else out <= ~inp;
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endmodule
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module foo(clk, rst, inp, out);
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(* this_is_the_master_clock *)
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input wire clk;
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input wire rst;
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input wire inp;
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output wire out;
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bar bar_instance (clk, rst, inp, out);
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initial begin
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$display("PASSED");
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end
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endmodule
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