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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
17 lines
332 B
Verilog
17 lines
332 B
Verilog
module top;
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wire [3:0] array [1:0];
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integer sel;
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assign array[0] = 4'h0;
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assign array[1] = 4'h1;
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initial begin
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#1;
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$display(" %h %h", array[0], array[1]);
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// This is only a problem for a wire (net array)!
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sel = 0;
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$display(" %h %h", array[sel], array[sel+1]);
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$display("PASSED");
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end
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endmodule
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