mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
129 lines
3.1 KiB
Verilog
129 lines
3.1 KiB
Verilog
// tests using array elements as indices/selects in an array lval select
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`timescale 1ns/100ps
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module tb;
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reg [7:0] a[7:0];
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real r[7:0];
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wire [2:0] idx[7:0];
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genvar g;
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for (g = 0; g < 8; g=g+1)
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assign idx[g] = g;
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reg pass;
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integer i;
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initial begin
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pass = 1'b1;
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// zero everything out
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for (i = 0; i < 8; i = i + 1) begin
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a[i] = 8'h0;
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r[i] = 0.0;
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end
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// test using one in a part select
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a[1][idx[1]*4 +: 4] = 4'ha;
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if (a[1] != 8'ha0) begin
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$display("FAILED part select, expected a0, got %x", a[1]);
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pass = 1'b0;
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end
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// test using one in an index
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a[idx[2]] = 8'hbc;
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if (a[2] != 8'hbc) begin
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$display("FAILED word index, expected bc, got %x", a[2]);
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pass = 1'b0;
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end
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// and now both...
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a[idx[3]][idx[0]*4 +: 4] = 4'hd;
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if (a[3] != 8'h0d) begin
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$display("FAILED word index and part select, expected 0d, got %x", a[3]);
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pass = 1'b0;
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end
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// non-blocking, in part select
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a[4][idx[1]*4 +: 4] <= 4'he;
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if (a[4] != 8'h00) begin
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$display("FAILED NB assign with part select 1, expected 00, got %x", a[4]);
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pass = 1'b0;
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end
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#0.1;
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if (a[4] != 8'he0) begin
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$display("FAILED NB assign with part select 2, expected e0, got %x", a[4]);
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pass = 1'b0;
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end
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// non-blocking, in index
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a[idx[5]] <= 8'h12;
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if (a[5] != 8'h00) begin
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$display("FAILED NB assign with word index 1, expected 00, got %x", a[4]);
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pass = 1'b0;
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end
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#0.1;
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if (a[5] != 8'h12) begin
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$display("FAILED NB assign with word index 2, expected 12, got %x", a[4]);
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pass = 1'b0;
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end
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// non-blocking, index and part select
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a[idx[6]][idx[0]*4 +: 4] <= 4'h3;
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if (a[6] != 8'h00) begin
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$display("FAILED NB assign with both 1, expected 00, got %x", a[4]);
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pass = 1'b0;
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end
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#0.1;
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if (a[6] != 8'h03) begin
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$display("FAILED NB assign with both 2, expected 03, got %x", a[4]);
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pass = 1'b0;
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end
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// NB, both, with a delay
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a[idx[7]][idx[1]*4 +: 4] <= #(idx[1]) 4'h4;
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#0.1;
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if (a[7] != 8'h00) begin
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$display("FAILED NB assign with both and delay 1, expected 00, got %x", a[4]);
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pass = 1'b0;
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end
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#1.1;
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if (a[7] != 8'h40) begin
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$display("FAILED NB assign with both and delay 2, expected 40, got %x", a[4]);
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pass = 1'b0;
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end
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// real array index
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r[idx[0]] = 1.1;
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if (r[0] != 1.1) begin
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$display("FAILED real word, expected 1.0, got %f", r[0]);
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pass = 1'b0;
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end
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// NB to real array
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r[idx[1]] <= 2.2;
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if (r[1] != 0.0) begin
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$display("FAILED NB assign real word 1, expected 0.0 got %f", r[1]);
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pass = 1'b0;
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end
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#0.1;
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if (r[1] != 2.2) begin
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$display("FAILED NB assign real word 2, expected 2.2 got %f", r[1]);
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pass = 1'b0;
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end
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// NB to real array with delay
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r[idx[2]] <= #(idx[2]) 3.3;
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#1.1;
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if (r[2] != 0.0) begin
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$display("FAILED NB assign with delay to real word 1, expected 0.0 got %f", r[1]);
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pass = 1'b0;
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end
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#1.0;
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if (r[2] != 3.3) begin
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$display("FAILED NB assign with delay to real word 2, expected 3.3 got %f", r[1]);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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