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https://github.com/steveicarus/iverilog.git
synced 2026-08-28 16:53:45 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
20 lines
580 B
Verilog
20 lines
580 B
Verilog
module top;
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integer lp;
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reg [7:0] array [2:0];
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initial begin
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// We can use the following to dump arrays. We can not dump
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// a whole array with this statment "$dumpvars(0, array);".
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//
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// $dumpvars is special in that it converts a variable array
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// select &A<array, index> into a constant array select.
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// This is needed to make the following work as expected.
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$dumpfile("work/array_dump.vcd");
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for (lp = 0; lp < 3; lp = lp+1) $dumpvars(0, array[lp]);
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#1;
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array[0] = 8'hff;
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array[1] = 8'h00;
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array[2] = 8'h55;
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end
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endmodule
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