60 lines
1.0 KiB
Verilog
60 lines
1.0 KiB
Verilog
module test;
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integer a, b, c;
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integer fd1, fd2, fd3;
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reg [64*8:1] str;
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initial begin
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a = 0;
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b = 0;
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c = 0;
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fd1 = $fopen("log/fmonitor1.log1", "w");
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fd2 = $fopen("log/fmonitor1.log2", "w");
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$fmonitor(fd1, "@%0t a = %0d", $time, a);
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$fmonitor(fd2, "@%0t b = %0d", $time, b);
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repeat (5) begin
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#1;
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a = a + 1;
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b = b + 1;
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c = c + 1;
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end
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$fclose(fd1);
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fd3 = $fopen("log/fmonitor1.log3", "w");
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$fmonitor(fd3, "@%0t c = %0d", $time, c);
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repeat (5) begin
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#1;
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a = a + 1;
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b = b + 1;
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c = c + 1;
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end
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$fclose(fd2);
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$fclose(fd3);
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$display("log1:");
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fd1 = $fopen("log/fmonitor1.log1", "r");
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while ($fgets(str, fd1)) begin
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$write("%0s", str);
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end
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$fclose(fd1);
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$display("log2:");
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fd2 = $fopen("log/fmonitor1.log2", "r");
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while ($fgets(str, fd2)) begin
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$write("%0s", str);
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end
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$fclose(fd2);
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$display("log3:");
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fd3 = $fopen("log/fmonitor1.log3", "r");
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while ($fgets(str, fd3)) begin
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$write("%0s", str);
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end
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$fclose(fd3);
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$finish(0);
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end
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endmodule
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