Stephen Williams 5a6d07ff9f Emit Verilog stubs for entities ... The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.		2011-01-18 17:03:51 -08:00
..
Makefile.in	Emit Verilog stubs for entities	2011-01-18 17:03:51 -08:00
StringHeap.cc	Parse create entities with ports	2011-01-18 17:03:51 -08:00
StringHeap.h	Parse create entities with ports	2011-01-18 17:03:51 -08:00
compiler.cc	Parse create entities with ports	2011-01-18 17:03:51 -08:00
compiler.h	Emit Verilog stubs for entities	2011-01-18 17:03:51 -08:00
entity.cc	Parse create entities with ports	2011-01-18 17:03:51 -08:00
entity.h	Emit Verilog stubs for entities	2011-01-18 17:03:51 -08:00
entity_elaborate.cc	Emit Verilog stubs for entities	2011-01-18 17:03:51 -08:00
lexor.lex	Parse create entities with ports	2011-01-18 17:03:51 -08:00
lexor_keyword.gperf	Parse create entities with ports	2011-01-18 17:03:51 -08:00
main.cc	Emit Verilog stubs for entities	2011-01-18 17:03:51 -08:00
parse.y	Parse create entities with ports	2011-01-18 17:03:51 -08:00
parse_api.h	Parse create entities with ports	2011-01-18 17:03:51 -08:00
parse_wrap.h	Parse create entities with ports	2011-01-18 17:03:51 -08:00
vhdlpp_config.h.in	Introduce shell of vhdlpp program.	2011-01-18 17:03:51 -08:00